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vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page 1 of 11 CD-700-SYNCE-25M0000000 complete vcxo based phase lock loop for synchronous ethernet jitter attenuation the vi cd-700 is a user-con gurable crystal based pll integrated circuit. it includes a digital phase detector, op-amp, vcxo and additional integrated functions for use in digital synchronization applications. loop lter software is available as well spice models for circuit simulation. 5 x 7.5 x 2 mm, smallest vcxo pll available ? two output frequencies (25 mhz and 50 mhz) ? integrated phase jitter < 600 fsec ? 5.0 or 3.3 vdc operation ? tri-state output ? holdover on loss of signal alarm ? vcxo with cmos outputs ? C40/85 ? 0c temperature range hermetically sealed ceramic smd package ? jitter attenuation ? clock smoothing ? synchronous ethernet, g.8262 ? features applications block diagram description cd-700 phase detector and los vcxo optional 2nd divider los (8) pho (3) opn (2) opout (1) vc (16) losin (4) datain (5) clkin (6) rclk (9) rdata (10) opp (15) gnd (7) vdd (14) hiz (12) out1 (13) out2 (11) rev: 15dec2009
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page 2 of 11 1. a 0.01uf and 0.1uf parallel capacitor should be located as close to pin 14 as possible (and grounded). 2. figure 2 de nes these parameters. figure 3 illustrates the equivalent ve gate ttl load and operating conditions under which these parameters are tested and speci ed. loads greater than 15 pf will adversely e ect rise/fall time as well as symmetry. 3. symmetry is de ned as (on time/period with vs=1.4 v for both 5.0 v and 3.3 v operation. figure 2. output waveform figure 3. out1, out2, rclk, rdata test conditions (25 50c) performance speci cations table 1. electrical performance parameter symbol min typical maximum units output frequency out 1, 3.3 v option out 2, 3.3v option 50.0 25.0 mhz mhz supply voltage 1 +3.3 v dd 2.97 3.3 3.63 v supply current i dd 63 ma output logic levels output logic high 2 output logic low 2 v oh v ol 2.5 0.5 v v output transition times rise time 2 fall time 2 t r t f 3.0 3.0 ns ns input logic levels input logic high 2 input logic low 2 v ih v il 2.0 0.5 v v loss of signal indication output logic high 2 output logic low 2 v oh v ol 2.5 0.5 v v nominal frequency on loss of signal output 1 output 2 75 75 ppm ppm symmetry or duty cycle 3 out 1 out 2 rclk sym1 sym2 rclk 40/60 45/55 40/60 % % % absolute pull range over operating temperure, aging, and power supply variations apr 100 ppm jitter generation - 25 mhz output (12khz - 20mhz bw) j 340 600 fsec-rms test conditions for apr (+3.3 v option) v c 0.3 3.0 v gain transfer kv positive phase detector gain +3.3 v kv 0.35 rad/v operating temperature t op -40/85 c control voltage leakage current i vcxo 1.0 a rev: 15dec2009
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page 3 of 11 stresses in excess of the absolute maximum ratings can permanently damage the device. functional operation is not implied at these or any other conditions in excess of conditions represented in the operational sections of this data sheet. exposure t o absolute maximum ratings for extended periods may adversely a ect device reliability. the cd-700 is capable of meeting the following quali cation tests: although esd protection circuitry has been designed into the the cd-700, proper precautions should be taken when handling and mounting. vi employs a human body model (hbm) and a charged device model (cdm) for esd susceptibility testing and design protection evaluation. esd thresholds are dependent on the circuit parameters used to de ne the model. reliability absolute maximum ratings table 2. absolute maximum ratings parameter symbol ratings unit power supply vdd 7 vdc storage temperature tstorage -55/125 0c soldering temperature/duration tpeak / tp 260 / 40 0c/sec clock and data input range clkin, datain gnd-0.5 to v dd +0.5 v table 3. environmental compliance parameter conditions mechanical shock mil-std-883, method 2002 mechanical vibration mil-std-883, method 2007 solderability mil-std-883, method 2003 gross and fine leak mil-std-883, method 1014, 100% tested resistance to solvents mil-std-883, method 2016 handling precautions table 4. predicted esd r$atings model minimum conditions human body model 1500 v mil-std 883, method 3015 charged device model 1000 v jesd 22-c101 rev: 15dec2009
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page 4 of 11 cd-700 theory of operation rev: 15dec2009 phase detector the phase detector has two bu ered inputs (datain and clkin) which are designed to switch at 1.4 volts. datain is designed to accept an nrz data stream but may also be used for clock signals which have a 50% duty cycle. clkin is connected to out1 or out2, or a divided version of one of these outputs. clkin and datain and are protected by esd diodes and should not exceed the power supply voltage or ground by more than a few hundred millivolts. the phase detector is basically a latched ip op/exclusive-or gate/di erential ampli er lter design to produce a dc signal proportional to the phase between the clkin and datain signals (see figure 4 for a block diagram and figure 5 for an open loop transfer curve). this will simplify the pll design as the designer does not have to lter narrow pulse signals to a dc level. under locked conditions the rising edge of clkin will be centered in the middle of the datain signal (see figure 6). figure 4. simpli ed phase detector block diagram the phase detector gain is 0.53v/rad x data density for 5volt operation and 0.35v/rad x data density for 3.3 volt opera- tion. data density is equal to 1.0 for clock signals and is system dependent on coding and design for nrz signals, but 0.25 could be used as a starting point for data density. the phase detector output is a dc signal for datain fre- quencies greater than 1 mhz but produces signi cant ripple when inputs are less than 200 khz. additional ltering is required for lower input frequencies applications such as 8khz (see figures 8 and 9 as examples). under closed loop conditions the active lter has a block- ing capacitor which provides a very high dc gain, so under normal locked conditions and input frequencies >1 mhz, pho will be about vdd/2 and will not vary signi cantly with changes in input frequency (within lock range). the control voltage (pin 16) will vary according to the input frequency o set, but pho will remain relatively constant. figure 5. open loop phase detecto transfer curve recovered clock and data alignment outputs the cd-700 is designed to recover an embedded clock from an nrz data signal and retime it with a data pattern. in this application, the vcxo frequency is exactly the same frequency as the nrz data rate and the outputs are taken o pin 9 (rclk), and pin 10 (rdata). under locked conditions, the falling edge of rclk is centered in the rdata pattern. also, there is a 1.5 clock cycle delay between datain and rdata. figure 6 shows the relationship between the datain, clkin, rdata and rclk. figure 6. clock and data timing relationships for the nrz data other rz encoding schemes such as manchester or ami can be accomodated by using a cd-700 at twice the baud rate.
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page 5 of 11 rev: 15dec2009 loss of signal, los and losin the los circuit provides an output alarm ag when the datain input signal is lost. the los output is normally a logic low and is set to a logic high after 256 consecutive clock periods on clkin with no detected datain transitions. this signal can be used to either ag external alarm circuits and/or drive the cd-700s losin input. when losin is set to a logic high, the vcxo control voltage (pin 16) is switched to an internal voltage which sets out1 and out2 to center frequency +/-75ppm. also, los automatically closes the op amp feedback which means the op-amp is a unity gain bu er and will produce a dc voltage equal to the +op amp voltage (pin 15), usually vdd/2. vcxo and absolute pull range (apr) speci cation the cd-700s vcxo is a varactor tuned crystal oscillator, which produces an output frequency proportional to the control voltag e (pin 16). the frequency deviation of the cd-700 vcxo is speci ed in terms of absolute pull range (apr). apr provides the user with a guaranteed speci cation for minimum available frequency deviation ov er all operating conditions. operating conditions include power supply variation, opera ting temperature range, and di erences in output loading and changes due to aging. a cd-700 vcxo with an apr of +/-50 ppm will track a +/-50 ppm reference source over all operating conditions. the fourth character of the product code in table 7 speci es absolute pull range (apr). please see vectrons web site (www.vectron.com) for the apr application note. apr is tested at 0.5 and 4.5 volts for the 5.0 volt option and 0.3 and 3.0 volts for the 3.3 volt opt ion. vcxo aging quartz oscillators typically exhibit a part per million shift in output frequency during aging. the major factors, which lead to this shift, are changes in the mechanical stress on the crystal and mass-loading on the crystal. as the oscillator ages, relaxation of the crystal mounting stress or transfer of environmental stress through the package to th e crystal mounting arrangement can lead to frequency variations. vi has minimized these two e ects through the use of a miniature at-cut strip resonator crystal which allows a superior mounting arrangement. this results in minimal relaxation and almost negligible environmental stress transfer. vi has eliminated the impact of mass loading by ensuring hermetic integrity and minimizing out-gassing by limiting the number of internal components through the use of asic technology. mass-loading on the crystal generally results in a frequency decreas e and is typically due to out-gassing of material within a hermetic package or from contamination by external material in a non- hermetic package. under normal operating conditions the cd-700 will typically exhibit 2 ppm aging in the rst year of operation. the device will then typically exhibit 1 ppm aging the following year with a logarithmic decline each year thereafter. frequency divider feature the lowest available vcxo out1 frequency is 1.000 mhz. to achieve lower frequencies, out1 is divided by a 2n counter (n = 1 to 8) and is the out2 frequency. the divider values (2, 4, 8, 16, 32, 64, 128 and 256) are set at the factory, so it is user selec table upon ordering only. in addition, a disabled out2 option is also available. to achieve 1.024 mhz, a cd-700 with out1 frequency equ al to 16.384 mhz and a divider value equal to 16 would be used. additional external divider circuits can be used to further lower or change the frequency. loop filter a pll is a feedback system which forces the output frequency to lock in both phase and frequency to the input frequency. while there will be some phase error, theory states there is no frequency error. the loop lter design will dictate many key parameters such as jitter reduction, stability, lock range and acquisition time. be advised that many textbook equations describing loop dynamics, such as capture range are based on ideal systems. such equations may not be accurate for real systems due to nonlinearities, dc o sets, noise and do not take into account the limited vcxo bandwidth. this section deals with some real world design examples. also, there is loop lter software on the vectron web site, plus a full sta of experienced applications engineers who are eager to assist in this process. common cd-700 pll applications are shown in figures 8, 9 (frequency translation), fi gure 10 (clock recovery) and figure 11 (clock smoothing).
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page 6 of 11 rev: 15dec2009 of primary concern to the designer is selecting a loop lter that insures lock-in, stability and provides adequate ltering of the input signal. for low input frequencies, a good starting point for the loop lter bandwidth is 10 hz (typical). an example would be translating an 8 khz signal to 44.736 mhz. figures 8 and 9 show 8khz to 44.736 mhz and 8khz to 19.440 mhz frequency translation designs. for high input frequencies, a good starting point for the loop lter bandwidth is 100 ppm times the input frequency. its fairly easy to set a low loop bandwidth for large frequency translations such as 8khz to 44.736mhz, but becomes more di cult for clock smoothing applications such as 19.440 mhz input and 19.440mhz output. in this example, 100ppm * 19.440mhz is approximately 2khz and this loop lter bandwidth may be too high to adequately reject jitter. a good way to resolve this is to lower the datain frequency such as dividing the input frequency down. the loop lter bandwidth becomes lower since 100ppm * datain is lowered. figure 11 shows an example for clock smoothing on a relatively high input frequency signal and maintaining a wide lock range. there is no known accurate formula for calculating acquisition time and so the best way to provide realisitc gures is to measure the lock time for a cd-700. by measuring the control voltage settling time, acquisiton time was measured in the range of 3-5 seconds for applications such as 8khz to 34.368 mhz frequency translation which is similar to the application in figures 8 and 9, to sub 10 milliseconds for nrz data patterns such as figure 10. it may be tempting to reduce the damping factor to 0.7 or 1.0 in order to improve acquisition time; but, it degrades stability and will not signi gantly improve acquisition time. a damping factor of 4 is fairly conservative and allows for excellent stability. some general quidelines for selecting the loop lter elements include: values should be less than 1megohm and at least 10kohm between the pho and opn, the capacitor should be low leakage and a polarized capacitor is acceptable, the r/cs should be located physically close to the cd-700 .the loop lter software available on the web site was written for 5 volt operation. a simple way to calculate values for 3.3 volt operation is to multiply the data density by 0.66 (3.3v / 5v). spice models are another design aid. in most cases a new pll cd-700 design is calculated by using the software and veri ed with spice models. the simple active spice model is shown in figure 7. loop lter values can be modi ed to suit the system requirements and application. there are many excellent references on designing plls, such as phase-locked loops, theory, design and applications, by roland e best (mcgraw-hill). figure 7. spice model *****cd-700 ac loop model vi 1 0 ac 1 ri 1 0 1k *****phase detector e1 2 0 1 0 1 (for closed loop response use: e1 2 0 1 12 1) r2 2 3 30k c1 3 0 60p *****phase detector gain=0.53 x data density (data density = 1 for clocks) for 5 volt operation and = 0.35 x data d ensity for 3.3 volt operation e2 4 0 3 0 .35 *****loop lter r1 4 5 60k c2 5 0 10p rf 5 6 90k cf 6 7 1.0u e3 7 0 5 0 C10000
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page 7 of 11 rev: 15dec2009 ***** vcxo, input bandwidth=50khz r5 7 8 160k c4 8 0 20p *****vcxo gain x 2 (example: 19.440 mhz x 100 ppm x 2 x ) e4 9 0 8 0 12214 *****1/s model r6 9 10 1000 c5 10 11 0.001u e5 11 0 10 0 C1e6 ****divide by n e6 12 0 11 0 1 r7 12 0 1k the bold numbers are user selectable r and c values that will vary depending on the application (see figure 11). layout considerations to achieve stable, low noise performance good analog layout techniques should be incorporated and a partial list is shown below . the cd-700 should be treated more like an analog device and the power supply must be well decoupled with a good quality rf 0.01 uf capacitor in parallel with a 0.1 uf capacitor, located as close to pin 14 as possible and connected to ground. in some cases, a pi lter such as a large capacitor (10uf) to ground, a series ferrite bead or inductor with 0.01 uf and 100 pf capacitor to ground to decouple the device supply. the traces for the out1, out2, rclk and rdata ouputs should be kept as short as possible. it is common practice to use a series resistor ( 50 to 100 ohms ) in order to reduce re ections if these traces are more than a couple of inches long. also out1, out2, rclk and rdata should not be routed directly underneath the device. the op-amp loop lter components should be kept as close to the device as possible and the feedback capacitor should be located close to the op-amp input terminal. the loop lter capacitor(s) should be low leakage (polarized capacitors are allowed). unused outputs should be left oating and it is not required to load or terminate them (such as an ecl or pecl output). loading unused outputs will only increase current consumption.
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page 8 of 11 rev: 15dec2009 application circuits figure 8. 25 mhz to 25 mhz jitter attenuation/clock smoothing the cd-700 includes a phase detector, op-amp, and a vcxo with an associated divideby function. its primary function is to reco ver a clock and align it with the original nrz (non return to zero) data pattern, but as a drop-in pll, it is commonly used for fre quency translation and to clean a jittered clock signal. in addition to itsexceptional functionality, the cd-700 is extremely exible as the loop lter can be tailored to the application and additional external divide-by circuitry extends the functionality. the above circuit has a 1 khz loop bandwidth. figure 9. typical phase noise performance for CD-700-SYNCE-25M0000000
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page 9 of 11 table 5. environmental compliance parameter symbol value preheat time t s 60 sec min, 180 sec max ramp up r up 3c/sec max time above 217c t l 60 sec min, 150 sec max time to peak temperature t amp-b 480 sec max time at 260c t p 20 sec min, 40 sec max ramp down r dn 6c/sec max figure 10. suggested ir pro le the device has been quali ed to meet the jedec standard for pb-free assembly. the temperatures and time intervals listed are based on the pb-free small body requirements. the temperatures refer to the topside of the package, measured on the package body surface. the cd-700 device is hermetically sealed so an aqueous wash is not an issue. rev: 15dec2009 table 6. tape and reel information tape dimensions (mm) reel dimensions (mm) a b c d e f g h i j k l #/reel 16 7.5 1.5 4 8 1.5 20.2 13 50 6 16.4 178 200 figure 11. tape and reel tape and reel
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page 10 of 11 table 7. pin functions pin symbol function 1 opout op-amp output 2 opn op-amp negative input 3 pho phase detector output 4 losin input (used with los) logic 0, vcxo control voltage is enabled. logic 1, vcxo control voltage (pin 16) is disabled and out1 and out2 are within +/-75 ppm of center frequency has internal pull-down resistor 5 datain phase detector input signal (ttl switching thresholds) 6 clkin phase detector clock signal (ttl switching thresholds) 7 gnd cover and electrical ground 8 los output (used with losin) logic 1 if there are no transitions detected at datain after 256 clock cycles at clkin. as soon as a transi- tion occurs at datain, los is set to a logic low. logic 0 = input frequency detected 9 rclk recovered clock 10 rdata recovered data 11 out2 divided-down vcxo output, or disabled 12 hiz input logic 0, out1, out2, rclk, rdata are set to a high impedance state. logic 1, out1, out2, rclk, rdata are active. has internal pull-up resistor 13 out1 vcxo output 14 v dd power supply voltage (3.3 v 10% or 5.0 v 10%) 15 opp op-amp positive input 16 v c vcxo control voltage figure 12. outline diagram rev: 15dec2009
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page 11 of 11 ordering information disclaimer vectron international reserves the right to make changes to the product(s) and or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. for additional information, please contact usa: vectron international 267 lowell road hudson, nh 03051 tel: 1.888.328.7661 fax: 1.888.329.8328 europe: vectron international landstrasse, d-74924 neckarbischofsheim, germany tel: +49 (0) 3328.4784.17 fax: +49 (0) 3328.4784.30 asia: vectron international 1f-2f, no 8 workshop, no 308 fenju road waigaoqiao free trade zone pudong, shanghai, china 200131 tel: 86.21.5048.0777 fax: 86.21.5048.1881 cd - 700 - synce - 25m0000000 product family cd: clock and data recovery package 700: 5.0 x 7.5 x 2.0mm input 3.3 vdc 10% output cmos/hcmos/acmos operating temperature -40 to 85 c absolute pull range 100 ppm out2 frequency out1 frequency 50 mhz rev: 15dec2009

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